The present invention relates to a semiconductor memory circuit.
When data are read from a non-volatile semiconductor memory circuit such as a flash memory, a logical level of the data to be read is determined according to a current value of a memory cell to be read. A circuit that determines the logical level based on a current distribution or a current difference (hereinafter referred to as a current window) of a memory cell between logical levels is called a sense amplifier. In addition, the current of the memory cell to be read flows to the sense amplifier via a bit line that connects to the memory cell (refer to Patent References 1 and 2).
FIG. 19 is a block diagram, which schematically shows a configuration of a conventional NOR semiconductor memory circuit 1000. FIG. 20 is a circuit diagram of memory cell arrays 120 and a multiplexer 130 of the semiconductor memory circuit 1000. As shown in FIGS. 19 and 20, the semiconductor memory circuit 1000 includes an M number of the memory cell arrays 120, which include a plurality of memory cells arranged in rows and columns (e.g., MC00, . . . , MC27, . . . , MCN0, . . . , MCN7); a multiplexer 130, which includes a plurality of transistors (e.g., transistors 130_0a, 130_0b, 130_1a, 130_1b, 130_2a, 130_2b, . . . ); and sense amplifiers SA0 and SA1.
In the semiconductor memory circuit 1000, COMMON is a common voltage source of the memory cells. DS[2M−1:0] (i.e., DS0, . . . , DS(2M−1)) are sub bit line selection signals applied to control terminals of transistors between the common voltage source COMMON and the sub bit lines (transistors 120_0, 120_2, 120_4, 120_6, and 120_8 are shown in FIG. 20). SS[M−1:0] (i.e., SS0, . . . , SS(M−1)) are sub bit selection signals applied to control terminals of transistors (121_1, 121_3, 121_5, 121_7, . . . are shown in FIG. 20) between the main bit lines and the sub bit lines. Y[K−1:0] (i.e., Y0, . . . , Y(K−1)) are main bit selection signals applied to control terminals of transistors (transistors 130_0a, 130_0b, 130_1a, 130_1b, . . . in the configuration 130 of FIG. 20) between the sense amplifiers SA0 and SA1 and the main bit lines.
WL[N×M−1:0] (i.e., WL0, . . . , WL (N×M−1)) are word lines. ICELL0 and ICELL1 are current values of memory cell to be read, and respectively flow to the sense amplifiers SA0 and SA1. The sense amplifiers SA0 and SA1 determine the logical levels of the memory cells to be read from the current values ICELL0 and ICELL1, and the determination results are output to output terminals DOUT0 and DOUT1. Here, “M” is the number of the memory cell arrays 120. “N” is the number of word lines provided in each memory cell array 120. “K” is the number of main bit selection signals Y (the number of signals) to select main bit.
SBL[8:0] (i.e., SBL0, . . . , SBL8) are sub bit lines, and MBL[3:0] (i.e., MBL0, . . . , MBL3) are main bit lines. The M number of the memory cell arrays 120 are connected to the main bit lines MBL[3:0]. To select a sub bit line in each memory cell array 120, a sub bit line selection signal that is different from others (one of SS[M−1:0]) is applied. Transistors indicated with prefix “MC” (e.g. MC00, . . . , MC27, . . . ) are memory cells.
As indicated as the memory cell arrays 120 in FIG. 20, each NOR memory cell array generally includes a plurality of word lines WL0, WL1, . . . , WLN to connect with gate terminal(s) of the memory cell and a plurality of sub bit lines SBL0, SBL1, . . . to connect with source terminal(s) or drain terminal(s) (hereinafter referred to as “diffusion layer(s)”), which are arranged in a lattice pattern. The memory cells MC00, . . . , MC27, . . . are usually disposed at every intersection of the respective word lines and bit lines.
In this case, the memory cell may be, for example, is configured having a P-type substrate region, a gate oxide film provided on the P-type substrate region, gate terminals (floating gates) provided on the gate oxide film, and a pair of N-type diffusion regions (diffusion layers) having a p-type substrate region therebetween. A memory cell to read may be selected by first selecting a word line to connect with a gate terminal of a memory cell to be read, connecting a bit line to connect with one of the diffusion layer to the sense amplifier SA0 or the sense amplifier SA1, and then connecting the other diffusion layer to the common voltage source COMMON.
The voltages of the sub bit lines SBL0, SBL1, . . . may vary depending on the presence of connection to the sense amplifier SA0 or SA1, the state of a memory cell to connect, and other factors. Therefore, even at sub bit lines that are not selected, transient voltage fluctuation occurs. In addition, voltages of the sub bit lines SBL0, SBL1, . . . are affected by voltage fluctuation of the adjacent sub bit lines depending on the coupling capacity. This influence brings the current, which is different from the original one of the memory cell to be read, to the selected sub bit line. As a result, the current window may vary or decrease, so that it is preferred to reduce the influence from the adjacent sub bit lines.
FIG. 21 is a diagram to explain a data reading operation of a conventional semiconductor memory circuit. From now on, the data reading operation of the semiconductor memory circuit 1000 will be described referring to FIG. 21. Here, a case of selecting the memory cells MC02 and MC05 will be described. When the word line WL0 is selected in the memory cell array 120, the memory cells MC00, MC01, . . . , MC07 in the row that contains the memory cells MC02 and MC05 are electrically connected. When the sub bit line selection signal DS1 is selected, the common voltage source COMMON becomes connected to one of the diffusion layers of the memory cell MC02 via the transistor 120_2 and the sub bit line SBL2, and the common voltage source COMMON becomes connected to one of the diffusion layers of the memory cell MC05 via the transistor 120_6 and the sub bit line SBL6.
When the sub bit line selection signal SS0 is selected, the main bit line MBL1 connects to the other diffusion layer of the memory cell MC02 via the sub bit line SBL3 and the transistor 121_3, and the main bit line MBL2 connects to the other diffusion layer of the memory cell MC05 via the sub bit line SBL5 and the transistor 121_5. When the main bit line selection signal Y1 is selected in the multiplexer 130, the main bit line MBL1 connects to the sense amplifier SA0 via the transistor 130_1a, and the main bit line MBL2 connects to the sense amplifier SA1 via the transistor 130_1b. 
With this operation, the memory cells MC02 and MC05 becomes in the selected states, currents of ICELL0 and ICELL01 flow to the sense amplifiers SA0 and SA1, respectively. The sense amplifier SA0 outputs the logic level determined from the current value ICELL0 to the output terminal DOUT0, and the sense amplifier SA1 outputs logic level determined from the current value ICELL1 to the output terminal DOUT1.
Here, for selecting the αth (α=0, 1, 2, . . . , M−1) sub bit line selection signal SSα and a main bit line selection signal Y(2n−2) that is with even number (here, n=1, 2, . . . ), (α×2+0)th sub bit line selection signal DS (α×2) is selected, and for selecting main bit line selection signal Y(2n−1) that is with an odd number, (α×2+1)th sub bit line selection signal DS(α×2+1) is selected.
As described above, the semiconductor memory circuit 1000 employs the circuit configuration, in which a pair of adjacent main bit lines (e.g. MBL1 and MBL2 in FIG. 21) is selected at the same time and then the respective main bit lines are connected to the sense amplifiers SA0 and SA1. Since the voltages of the bit lines connected to the sense amplifiers SA0 and SA1 become stabilized, it is possible to reduce the influences among the pair of adjacent main bit lines, sub bit lines connected to the pair of main bit lines, and the sub bit lines that are located between the sub bit lines connected to the main bit lines.
For example, by selecting the main bit line selection signal Y1 so as to select the pair of adjacent main bit lines MBL[2:1] at once, it is possible to reduce influences among the main bit lines MBL2 and MBL 1, the sub bit lines SBL5 and SBL3, and the sub bit line SBL4.    Patent Reference 1: Japanese Patent Publication No. 2006-309811    Patent Reference 2: International Patent Application No. 2006/035502
In these years, since the wiring intervals of bit lines becomes smaller due to finer memory cell configurations of these years, the coupling capacity between the bit lines has increased and thereby the influences of the voltage fluctuation of the adjacent bit lines on the current values have also increased. On the other hand, since the memory cells become finer and multi-valued, the current difference between the current windows decreases. Accordingly, influences of the current value change due to voltage fluctuation of the bit lines on the current windows have relatively increased.
In the conventional techniques, by selecting a pair of adjacent main bit lines at once, the influences between adjacent bit lines are reduced by each other. On the other hand, the main bit lines, which are next to outside the selected pair of main bit lines, are connected to the common voltage source via a non-selected memory cell. Since driving force of a memory cell is relatively small, when the voltage of the main bit lines that are adjacent outside significantly fluctuates, the voltage fluctuation due to charge/discharge to/from the common voltage source via the non-selected memory cell continues during the reading operation. As already described above, this voltage fluctuation affects the current windows of the selected memory cell.
For example, when a pair of adjacent main bit lines is selected and connected to a sense amplifier, sharp voltage fluctuation occurs on those main bit lines. Because of this, voltage fluctuation also occurs on the adjacent main bit lines outside the selected pair of the main bit lines. When the voltage fluctuation is relatively significant and occurred sudden, there is influence on the current window of the selected memory cell.
In view of the problems described above, an object of the present invention is to solve the problems in conventional techniques, and is to provide a semiconductor memory circuit, which can reduce the voltage fluctuation of main bit lines that are adjacent outside a selected pair of main bit lines.
Further objects and advantages of the invention will be apparent from the following description of the invention.